targets=top.vhdl,top.vvp,top.fpga,s p a c e.fpga
verilog=iverilog

[top.fpga]
type=object
vflags=-tfpga
sources=top.v

[top.vhdl]
type=object
vflags=-tvhdl
sources=top.v

[top.vvp]
type=object
sources=top.v

[s p a c e.fpga]
type=object
vflags=-tfpga
sources=s p a c e.v
