configure

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targets=top.vhdl,top.vvp,top.fpga,s p a c e.fpga
verilog=iverilog
[top.fpga]
type=object
vflags=-tfpga
sources=top.v
[top.vhdl]
type=object
vflags=-tvhdl
sources=top.v
[top.vvp]
type=object
sources=top.v
[s p a c e.fpga]
type=object
vflags=-tfpga
sources=s p a c e.v